Cyclone CoCo Prototype Programmers Reference

 

Last updated on 11-26-2017.

Please check this document frequently for possible changes before releasing your work.

Programming your Terasic DE0-Nano to become a CoCo

Latest Terasic DE0-Nano JTAG Indirect Configuration
http://www.cococommunity.net/downloads/Cyclone/CycloneCoCo_081617a.jic

The Cyclone CoCo is implemented as real logic and does not run under an emulator or parent operating system. It’s the closest thing to an actual CoCo as you can get.

 

Some additions to the GIME Chip

  • 1MB MMU
  • Rate control overrides SAM, throttles CPU to x1, x2, x4, x8 E/Q clocks (up to ~7 Mhz)
  • Up to 80×60 text
  • Scanline effect
  • Semi-graphics 6,8,12,24
  • 512 total colors possible
  • Special 256-color mode can use palette or DAC
  • Max graphics resolution of 640×480 256 colors
  • Ability to change video address mid-frame
  • Ability to read the video address registers ($FF9D-$FF9E)
  • 16 palette groups for defining 256 colors using the standard palette registers
  • Frame rate automatically adjusts if SRAM is too slow for the desired video mode
  • GPU interrupt when command is complete
  • Multiple split-screen effects possible using clever IRQ/FIRQ programming
  • RAM rate control (experimental)

 

CoCoNet-Capable System

Both the Disk BASIC ROM and the OS-9 drive mentioned below support the CoCoNet virtual drive system as an option (that is, not required) for moving files between your PC and the Cyclone CoCo. You might want to install a recent version of the CoCoNet GUI server on your Windows PC:

http://www.cococommunity.net/downloads/CoCoNetServer+2017.zip

 

FAT32 SD Card Required for DOS

For something to start with, two disk images you might want to copy to your fresh FAT32 card are:

http://www.cococommunity.net/downloads/Cyclone/dos.dsk <– Some utilities/demos.

http://www.cococommunity.net/downloads/Cyclone/os9.zip <– 128MB NitrOS-9 drive compiled by Bill Nobel and Roger Taylor.

Until further notice any time you manipulate your SD card files using a Windows or Linux system you should DEFRAGMENT the card’s file structure. Windows and Linux both have a simple procedure that only takes a few seconds in most cases. If you’re not sure whether your card needs defragmenting, that’s a good time to do it. Eventually the Cyclone SD controller will handle fragmented files and we won’t have to worry about this sort of thing.

 

Extended Video Control Register – $FF10 (65296) read/write

  • bits 7,6 — Video clock: 00=x1, 01=x2, 10=x4, 11=x8
  • bit 5 —– Double-height video (x2 vertical resolution) requires twice as much video RAM and may slow down frame rate
  • bit 4 —– Disable raster effects, turn off CRT mode, gives better quality in high-res modes
  • bit 3 —– Allow ‘GIME CRES=3’ to enable the 256-color mode
  • bit 2 —– Allow video address to be changed mid-frame (pending)
  • bit 1 —–
  • bit 0 —– Allow SG6 graphics in CoCo 1/2 mode, allow SG4/SG8/SG16 graphics in CoCo 3 mode (pending)

Changing the video address mid-frame using clever IRQ/FIRQ programming, various split-screen effects could be possible.

 

Rate Control Register – $FF11 (65297) read/write

  • bit 7 —— Enable master rate control, overrides SAM and GIME registers
  • bits 5..3 — RAM rate: 00=x1, 01=x2, 10=x4, 11=x8, etc.
  • bits 2..0 — CPU rate: 00=x1, 01=x2, 10=x4, 11=x8, etc.

Notes about the SRAM chips and what they can yield on this system:

  • (14.318182 Mhz CPU) + (14.318182 Mhz video) requires at least 34.920634477198ns SRAM.
    Why? Because the total bandwidth is 28.636364 MHz.
    The next faster SRAM is 10ns.
  • (7.159091 MHz CPU) + (7.159091 MHz video) = (total = 14.318182 MHz) requires at least 69.841268954397ns SRAM.
    Why? Because the total bandwidth is 14.318182 MHz.
    The next faster SRAM is 55ns.
    With this SRAM an additional SDRAM framebuffer is used to achieve unsupported video resolutions but at lower frame rates.
  • There doesn’t appear to be any benefit to using 35ns or 45ns SRAM.
  • At this time the SRAM controller in the FPGA chip is hard-coded for one type of SRAM. Therefore, a different configuration file will be needed if and when you switch to 10ns.
  • The original Dewberry and some of the first NanoMate daughter boards have soldered-in 70ns SRAMs and are no longer supported. You can cut those SRAMs off of the board and install sockets for faster chips instead of throwing the whole board away. All new NanoMate boards should have sockets installed until we move to an SMT version of the board with 10ns SRAM which I believe will be the fastest we can expect, and this is extremely fast for a CoCo system!

 

System Control – $FF12 (65298) read/write

  • bit 2 — 512K-only RAM mode (pending)
  • bit 1 — Insert virtual cartridge (pending)
  • bit 0 — Enable writes to ROM (pending)

In CoCo 3 mode, ROMs are usually hidden or converted to RAM until the system is power-cycled. For whatever purpose, you can alter the actual ROM memory while it’s mapped into the CPU space using this register. Soon, a certain F-key will simulate the insertion of a cartridge, or you can use this register to do it programmatically. Soon, pressing a certain F-key during a CoCo Reset will enable the 512KB-only mode, or you can use this register to do it programmatically.

 

Burden-Free Mouse/Joystick – $FF14..$FF17 (65300-65303) read

  • $FF14 — Horizontal coordinate, bits 15..8
  • $FF15 — Horizontal coordinate, bits 7..0
  • $FF16 –- Vertical coordinate, bits 15..8
  • $FF17 — Vertical coordinate, bits 7..0

You want the mouse or joystick to work in any game or software, hi-res or lo-res mode, automatically. No problem! Besides the convenience of reading the tracker coordinates directly, the regular 6-bit ADC and various hi-res adapters are automatically supported and utilized no matter if you’re using a PS/2 mouse or real CoCo joysticks or CoCo mouse. If this feature doesn’t amaze you, nothing will.

 

 

Palette Control – $FF1B (65307) read/write

  • Bit 7 —— Disable palette, enable DAC mode (RRRGGGBB)
  • Bit 6 —–– Enable extended palette
  • Bits 5..4 –- Extended palette format (pending)
    • 0 — xxRGBRGB (Standard CoCo 3 palette)
    • 1 — xIRGBRGB (Adds intensity bit to standard CoCo 3 palette)
    • 2 — RGRGBRGB (3-3-2 format 1)
    • 3 — RRRGGGBB (3-3-2 format 2)
  • Bits 3..0 -– Palette Group 0-15

The Extended Palette switch combines several functions. All non 256-color modes can get their colors from one of 16 different palettes selected by the Palette Group Register. If this switch is off then the normal 16-color palette (group #0) will be displayed, otherwise the selected group will be used. This switch also enables writing more range bits into the palette slots using the selected format such as xIRGBRGB format where if I is the intensity of RGBRGB. In order to set up the 256-color palette, the normal CoCo 3 palette registers are used along with a group number. By enabling the Extended Palette and changing the Palette Group register, 16 different 16-color palettes can be configured. Furthermore, they can be switched very quickly making many special effects possible depending on when or where you change the palettes. Group 0 is the default when the Extended Palette isn’t enabled. The 256-color scheme of the Cyclone includes an 8-bit DAC mode where one byte is one pixel, and a palette mode where the video byte equals the palette slot. Because the CoCo 3 has only 16 palette registers, a Palette Group register has been added to the Cyclone to give a total of 16 standard GIME palettes totaling 256 color codes. So, 256 out of 512 colors can be shown at one time. Naturally the DAC mode and palette mode have their pros and cons depending on your software, game, or demo.

 

Color Palette – $FFB0-$FFBF (65456-65471) read/write

16 slots of colors in the format defined by the Palette Control register.

 

Telemux – $FF1F (65311) read/write

3 serial ports, 2 wireless devices.
[CoCo software <-> port <-> device 0-3 <-> wireless/wired link <-> remote device <-> remote port <-> remote software]

  • Device bits 7..6 –- Device for 6551 ACIA $FF6C port
  • Device bits 5..4 –- Device for 6551 ACIA $FF68 port
  • Device bits 3..2 — Device for serial/printer port
  • Bit 1 —— Device 2 baud rate doubler
  • Bit 0 —— Device 1 baud rate doubler

Device 0 = The ‘Bit Bucket’
Device 1 = HC-05 bluetooth module, or any other module connected to the HC-05 header
Device 2 = ESP8266-01 WIFI module, or any other module connected to the 8266 header
Device 3 = (pending) User I/O header (3.3V)

Example Configurations:

 
  • 00100100
    Wire $FF6C ACIA to ‘Bit Bucket’
    Wire $FF68 ACIA to WIFI
    Wire bitbanger to HC-05
  • 10010000
    Wire $FF6C ACIA to WIFI
    Wire $FF68 ACIA to HC-05
    Wire bitbanger to ‘Bit Bucket’
  • 01100000
    Wire $FF6C ACIA to HC-05
    Wire $FF68 ACIA to WIFI
    Wire bitbanger to ‘Bit Bucket’

IMPORTANT NOTE: As of 8-19-2017, this register is changed without notice by DOS if the CoCoNet drives are accessed. DOS wires the HC-05 to the $FF6C ACIA. The OS-9 CoCoNetRBF driver as of uses $FF68 but doesn’t automatically wire it up the HC-05. Other drivers that use $FF68 could conflict with CoCoNetRBF. I plan to have the driver wire the HC-05 to the port specified in the descriptors and also set the Telemux register automatically. Ultimaterm 4.x has a secret 115200 bps mode – set the baud rate to “450” and choose RS-232 Pack. If the baud rate doubler is enabled, up to 230400 bps can be achieved over the ACIAs.

 

3.3V User I/O Port – $FF1C (65308) read/write

  • Bit 4 — Output through user header UOUT1
  • Bit 3 — Output through user header UOUT0
  • Bit 1 — Input through user header UIN1
  • Bit 0 — Input through user header UIN0

 

ESP8266-01 WIFI – $FF1D (65309) read/write

  • Bit 7 — GPIO2 direction
  • Bit 6 — GPIO0 direction
  • Bit 3 — GPIO2 state
  • Bit 2 — GPIO0 state
  • Bit 1 — CHPDn
  • Bit 0 — RESETn

 

HC-05 Bluetooth – $FF1E (65310) read/write

  • Bit 2 — BT_EN, BT_KEY
  • Bit 0 — BT_STATE

Some HC-05 modules might be configured slightly different than others. Some require the BT_EN pin to be held high during power-up in order to go into programming mode. Others need BT_EN to be held high during normal use for communications. To learn what the purpose of BT_EN is for your particular HC-05 style, please read the module instructions thoroughly. There are several ways to enable BT_EN: 1) hold down F12 on your keyboard to temporarily enable BT_EN or, 2) enable bit 2 of this register.

 

SDC Data Register – $FF70 (65392) read/write

 

SDC Status Register – $FF71 (65393) read

  • Bit 7 –- Byte ready to send
  • Bit 6 –- Controller busy
  • Bit 5 –- Sector Transfer Busy
  • Bit 4 –- Valid FAT32 card
  • Bit 3 –- Disk image found/mounted
  • Bit 2 –- SD card class
    • 0 – SDSC
    • 1 – SDHC
  • Bit 1
  • Bit 0 -– Write Busy

 

SDC Command Register – $FF71 (65393) write

  • Read Sector
    • Bit 7 – 0
    • Bit 6 – 0
    • Bit 5 – 0
    • Bit 4 – 0
    • Bit 3 – x
    • Bit 2 – x
    • Bit 1 – x
    • Bit 0 – 0
  • Write Sector
    • Bit 7 – 0
    • Bit 6 – 0
    • Bit 5 – 0
    • Bit 4 – 0
    • Bit 3 – x
    • Bit 2 – x
    • Bit 1 – x
    • Bit 0 – 1
  • Reset Controller
    • Bit 7 – 0
    • Bit 6 – 0
    • Bit 5 – 1
    • Bit 4 – 1
    • Bit 3 – x
    • Bit 2 – x
    • Bit 1 – x
    • Bit 0 – x
  • Mount Image
    • Bit 7 – 0
    • Bit 6 – 0
    • Bit 5 – 1
    • Bit 4 – 0
    • Bit 3 – x
    • Bit 2 – x
    • Bit 1 – x
    • Bit 0 – x
  • Direct Mode
    • Bit 7 – 1
    • Bit 6 – 1
    • Bit 5 – 0
    • Bit 4 – 0
    • Bit 3 – x
    • Bit 2 – x
    • Bits 1..0 – Drive #
  • Image Mode
    • Bit 7 – 1
    • Bit 6 – 0
    • Bit 5 – 0
    • Bit 4 – 0
    • Bit 3 – x
    • Bit 2 – x
    • Bits 1..0 – Drive #

 

All commands operate on the drive # specified in register $FF77 unless the drive # is specified in the command byte, as in Direct Mode and Image Mode.

Virtual Disk Mounting Tips: Poke the command byte (32), wait a few CPU cycles, go into a loop until the Sector Busy signal goes High, then send the 11 characters for the 8.3 filename of the virtual disk. After sending each character you should wait until bit #0 of the Status Register goes Low. After the filename has been sent you should go into a timed loop until the Busy signal goes Low at which time you can check the Disk Image Found bit to determine whether your image was mounted or not.

Direct mode and Image mode are Per Drive commands that tell the controller to access the card directly starting at LSN 0 or the currently-mounted virtual disk. Mounting an image will put the controller into Image Mode automatically. Switching to Direct Mode does not dismount any images. Therefore, you can switch between Direct and Image mode at will.

 

SDC LSN Register – $FF72-$FF75 (65394-65397)

$FF72

LSN bits 23..16

$FF73

LSN bits 15..8

$FF74

LSN bits 7..0

$FF75

LSN bits 31..24

Read-only

This is a dual-purpose register! The CoCo is limited to 24-bit LSNs in SDC mode, and up to 256 tracks * 18 sectors in FDC mode. This range is within the mounted image being accessed which could reside anywhere on a 32-bit SD card. To find out where your image is located on the card, mount the image then do a read of LSN $000000 if SDC mode, or track #0, sector #1 if FDC mode, then read all 4 of the SDC LSN registers back to see the actual SD location of the image (Pending feature).

 

SDC Drive Select – $FF77 (65399)
To be discontinued. To be moved to the Command Register soon.

  • Bits 1..0 –- Drive # 0-3

 

IRQENR (Interrupt Request enable/status) – $FF92 (65426)

  • Bit 7 -– GPU command complete
  • Bit 6 —
  • Bit 5 -– GIME Timer
  • Bit 4 –- Horizontal Border
  • Bit 3 –- Vertical Border
  • Bit 2 –- Serial data
  • Bit 1 –- Keyboard (leading edge-triggered)
  • Bit 0 –- Cartridge/6551

 

FIRQENR (Interrupt Request enable/status) – $FF93 (65427)

  • Bit 7 –- GPU command complete
  • Bit 6 — High-speed ADC?
  • Bit 5 -– GIME Timer
  • Bit 4 -– Horizontal Border
  • Bit 3 -– Vertical Border
  • Bit 2 -– Serial data
  • Bit 1 -– Keyboard (leading edge-triggered)
  • Bit 0 -– Cartridge/6551

 

AY-3-891x/YM2149 Sound Controller – $FF96-$FF97 (65430-65431)

  • $FF96 — Address and Data
  • $FF97 –- Control
    • Bits 7..2 — undefined
    • Bit 1 —— BC1
    • Bit 0 —— BDIR

BC2 is always wired High and requires no setting.

 

Orchestra-90CC – $FF7A-$FF7B (65402-65403)

  • $FF7A — 8-bit left channel DAC
  • $FF7B — 8-bit right channel DAC

The Orchestra-90CC circuitry attempts to duplicate the RCA jack outputs of the original cartridge. These outputs can be fed into a stereo amplifier and sound can be heard no matter what other sound or analog devices are being used by the CoCo. Therefore, if anything is POKED to these registers, the sound heard by the Cyclone CoCo will include these DAC outputs.

 

Disk Extended BASIC

For better compatibility with DOS and OS-9, the floppy drive controller circuit is tied to the SD card interface internally. All that’s really needed by DOS and OS-9 is to mount a virtual floppy disk in the FDC. This basically points to the top of the disk image on the SD card and then the FDC accesses the card instead of a real floppy disk.

To set up an SD card for use with the Cyclone, format the card as “FAT32” from Windows or Linux or any other device that can format an SD card. The card is now ready to hold thousands of floppy and hard drive image files that will work like the real drives on the Cyclone.

To boot into an OS-9 “disk” named “OS9.DSK” on the SD card:

  • DOS “OS9” or
  • DRIVE 0,”OS9″:DOS

To mount Sock Master’s demo disk and do a listing then run one of the demos:

  • DRIVE 0,”SOCK”
  • DIR
  • LOADM “BOINK”
  • EXEC

 

 

 

 

GPU (Graphics Processing Unit) – $FF30-$FF34 (65328-65332)

Prepare to be impressed with a new and extremely fast way of performing certain graphics and memory functions. How does it work? Enter DMA. A graphics processor core has been added that runs all the time in the background and can access the regular CoCo RAM whenever the CPU isn’t using it which is about 20% of the time when the CPU isn’t HALTed, or 100% of the time when the CPU is HALTed. In no-HALT mode all of the commands are completely transparent to the system and take up no extra time to perform. There is also an interrupt signal sent to the GIME whenever a command is complete, meaning you can cycle through a list of commands using the CoCo’s IRQ/FIRQ system and perform complex and lengthy operations that seem to be completely transparent to the CoCo.

The GPU only deals with bytes and therefore works best with the 256-color mode. If the Width or Height is Zero then operation is performed on contiguous memory of size (Width + Height), otherwise a rectangle area. If the Width and Height is Zero then operation is performed for a single source byte to a single destination byte.

Another awesome feature of the GPU is that it bypasses the CoCo 3’s MMU system and lets you specify the actual RAM addresses involed using the 24-bit Source and Destination registers.

IMPORTANT: When writing to the 24-bit GPU registers, a separate CPU instruction is required for each register BYTE. That is, a 16-bit value store to 2 of the register bytes at once is not supported at this time due to the nature of the GPU. Instead, do something like LDD #WIDTH, CLR REG+0, STA REG+1, STB REG+2.

  • $FF30 – Command register (write)
    • Bit 7 —— HALT CPU during command
    • Bit 6 —— Use transparency
    • Bits 4..0 – Command
  • $FF30 – Status register (read)
    • Bit 7 – Command is done
    • Bit 0 – GPU is busy
  • $FF31 – Register number (write)
  • $FF32..$FF34 – Register contents (write)
    • $FF32 – bits 23..16
    • $FF33 – bits 15..8
    • $FF34 – bits 7..0

 

GPU Commands

Working

Pending

00001 – Fill (fill a contiguous area of RAM or a rectangle area using BPR and DEST. If width or height is 0 then fill contiguous RAM.)

00000 – Null (Good for checking status of GPU or kick-starting an interrupt-driven sequence.)

00010 – Copy (copy SOURCE1 to DEST with limited logic such as NOT and XOR.)

00101 – Circle

00011 – Mix (logical mix SOURCE1 with SOURCE2 with results going to DEST.)

00111 – Flood

00100 – Line (uses DEST, Vector2 for offset, and should normally have Vector1 set to 0,0.)

 

01000 – Move (similar to Line command but no drawing.)

 
   
   

 

GPU Registers
* = pending

0 – LOGIC

  • Bits 7..4 – {operation} on Source
  • Bits 3..0 – Source {operation} Destination

0001 = OR
0010 = AND
0011 = NOT
0100 = XOR
0101 = NOR
0110 = XNOR
0111 = NAND

1 – COLOR

2 – TRANSPARENT

3 – RESOLUTION (pending)

4 – WIDTH (fill, copy, mix)

5 – HEIGHT (fill, copy, mix)

6 – VectorX (start vector for line, etc.)

7 – VectorY

8 – VectorX2 (end vector for line, etc.)

9 – VectorY2

10 – RADIUS (pending use for circle)

16 – SOURCE1 (starting address)

17 – BPR1 (bytes per row for fill, copy, mix source)

32 – SOURCE2 (address for mix)

33 – BPR2 (bytes per row for mix)

48 – DEST (destination address for copy, mix)

49 – BPR (bytes per row for copy, mix)

 
 
 
 

 

 

NanoMate GPIO1 

Cyclone IV Pin 

  

NanoMate GPIO1 

Cyclone IV Pin 

IR Data In 

T9 

  

SD CS 

F13 

User IN-C 

R9 

  

SD MOSI 

T15 

WIFI IO1 

T14 

  

SD CLK 

T13 

WIFI Reset 

R13 

  

SD MISO 

T12 

WIFI Receive 

R12 

  

DAC LDAC 

T11 

VCC5 

  

  

GND 

  

WIFI Transmit 

T10 

  

BT TX 

R11 

WIFI CHPD

P11 

  

BT RX 

R10 

VGA Blue 2 

N12 

  

BT KEY 

P9 

VGA Green 2 

N9 

  

BT STATE 

N11 

VGA Red 2 

L16 

  

DAC SCK 

K16 

VGA Blue 1 

R16 

  

DAC SDI 

L15 

VGA Green 1 

P15 

  

DAC CSN 

P16 

VGA Red 1 

R14 

  

SRAM CE2n 

N16 

VCC33 

  

  

GND 

  

VGA Blue 0 

N15 

  

WIFI IO0 

P14 

VGA Green 0 

L14

  

KEY CLK 

N14 

VGA Red 0 

M10 

  

KEY DATA 

L13 

VGA HSYNC 

J16 

  

MOUSE DATA 

K15 

VGA VSYNC 

J13 

  

MOUSE CLK 

J14 

 

 

NanoMate GPIO0 

Cyclone IV Pin 

  

NanoMate GPIO0 

Cyclone IV Pin 

User IN-B 

A8 

  

IO3 

D3 

User IN-A 

B8 

  

IO2 

C3 

SRAM A15 

A2 

  

IO1 

A3 

SRAM A17 

B3 

  

FRONT LED

B4 

SRAM A18 

A4 

  

SRAM A16 

B5 

VCC5 

  

  

GND 

  

SRAM A14 

A5 

  

SRAM WEn 

D5 

SRAM A12 

B6 

  

SRAM A13 

A6 

SRAM A7 

B7 

  

SRAM A8 

D6 

SRAM A6 

A7 

  

SRAM A9 

C6 

SRAM A5 

C8 

  

SRAM A11 

E6 

SRAM A4 

E7 

  

SRAM OEn 

D8 

SRAM A3 

E8 

  

SRAM A10 

F8 

SRAM A2 

F9 

  

SRAM CE1n 

E9 

VCC33 

  

  

GND

  

SRAM A1 

C9 

  

SRAM D7 

D9 

SRAM A0 

E11 

  

SRAM D6 

E10 

SRAM D0 

C11 

  

SRAM D5 

B11 

SRAM D1 

A12 

  

SRAM D4 

D11 

SRAM D2 

D12 

  

SRAM D3 

B12 


 

Leave a Reply